Modelsim pe se
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So your rising_edge condition is only valid one time. Then, in your testbench, like commented, you didn't make your clock change its state. It will take fewer elements to implement this. (If you don' t know what it is check there.) Since your process is synchronous to your clock CLK you need to put it into the sensitivity list.Īnother thing that might be useful (it 's more a suggestion than a real mistake) is to put any of your register's reset signal asynchronous (at least in the process) and if you want it synchronous you can still synchronize it at the top level. When creating your process instantiating your register you didn't specify any sensitivity list. There are some typical errors that you should understand and avoid first. UUT: entity work.REG_SYNC_12BIT port map (D_IN, CLK, EN, RST, D_OUT)
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testbench for register with 12 bit data width and synchronous resetĪrchitecture BEHAVIOUR of TESTBENCH_REG_SYNC_12BIT is register with 12 bit data width and synchronous reset UUT: entity work.MULTIPLEXER_4TO1_12BIT port map (SELECT_IN, D_IN_0, D_IN_1, D_IN_2, D_IN_3, D_OUT) Īssert false report "end of simulation" severity failure Signal SELECT_IN: bit_vector (1 downto 0) := "00" testbench for multiplexer for 4 inputs with 12 bit data width to 1 output with 12 bit data widthĮntity TESTBENCH_MULTIPLEXER_4TO1_12BIT isĪrchitecture BEHAVIOUR of TESTBENCH_MULTIPLEXER_4TO1_12BIT is multiplexer for 4 inputs with 12 bit data width to 1 output with 12 bit data widthĪrchitecture RTL of MULTIPLEXER_4TO1_12BIT isĭ_OUT <= D_IN_0 when SELECT_IN = "00" else I really can't find the problem in this code.
#Modelsim pe se code#
I tried to look at the wave forms but they change neither.įollowing I will send you the corresponding code for my 4x1-MUX (which simulates quite well) and code for my 12bit register with synchronous reset (which doesn't simulate correctly). Whenever I try to simulate nothing happens and the simulation doesn't finish at any point. The simulation for the multiplexer and demultiplexer works quite well but the testbench for the registers seems to simulate for ever. To test my code I tried to implement a testbench for each file. I wrote some files for a RTL-model such as multiplexer, demultiplexer and register. I'm very new to VHDL and got an issue with the simulation time in Modelsim PE Student Edition 10.4.